A digital signal computer, or digital signal processor (DSP), is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing and speech recognition. Digital signal processor applications are typically characterized by real time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Thus, designs of digital signal processors may be quite different from those of general purpose computers.
One approach that has been used in the architecture of digital signal processors to achieve high speed numeric computation is the Harvard architecture, which utilizes separate, independent program and data memories so that the two memories may be accessed simultaneously. This architecture permits an instruction and an operand to be fetched from memory in a single clock cycle. Frequently, the program occupies less memory space than the operands for the program. To achieve full memory utilization, a modified Harvard architecture utilizes the program memory for storing both instructions and operands. Typically, the program and data memories are interconnected with the core processor by separate program and data buses.
Digital signal processors may utilize architectures wherein two or more data words are stored in each row of memory and two or more data words may be provided in parallel to the computation unit. Such architectures provide enhanced performance, because several instructions and/or operands may be accessed in parallel.
Digital signal processors are frequently required to perform digital filter computations, wherein output signal samples of a digital filter are computed for specified input signal samples. In a finite impulse response (FIR) digital filter, filter coefficients are multiplied by data values representative of respective signal samples, and the products are combined to provide a filter output value. The data values are then shifted relative to the filter coefficients, and the process is repeated to provide data values representative of successive filter output signal samples. Such computations are difficult to perform efficiently in digital signal processor architectures wherein two or more data words are stored in each row of memory. In particular, complex software routines are required to perform the computations, because the data values are not easily aligned with the proper coefficients on each clock cycle.
Accordingly, there is a need for improved digital signal processor architectures in which these difficulties are overcome.